FinFET transistors have begun to replace traditional planar transistors in next generation devices due to the ability to enhance the control of current flowing between source and drain regions of the transistors at smaller nanometer nodes. Devices, such as memory structures, also benefit from the use of FinFET transistors because FinFET transistors have lower power and provide increased transistor density while enabling improved device performance.
Memory structures that use FinFET transistors remain susceptible to single event upsets (SEU), just like planar transistors. SEU may be caused by any number of factors. The failure rate associated with SEU events is commonly known as Soft Error Rate (SER), and the industrial metric used to quantify the SER of the circuit is known as FIT rate or FIT/Mb Soft Error Rate (SER). The complimentary random access memory (CRAM) FIT rate is characterized using JESD89A standards. However, the SER often undesirably increases as the size of memory structures continue to shrink.
FinFET transistors may be used in both front end circuits and back end circuits. However, the performance of the FinFET transistors is often dependent on whether the FinFET transistor is part of a front end or back end circuit. Thus, solutions for improving SER often cannot universally be applied to both front and back end circuits. Improving SER in front end circuits is particularly difficult due to high parasitics, particularly at high frequencies.
Thus, there is a need for an improved FinFET transistor suitable for front end circuits.